Software and Hardware Emulation System

ABSTRACT

A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. The method further comprising, when the system has not performed to the specification, determining one or more of the hardware and software portions to update for retesting.

BACKGROUND OF THE INVENTION

Matching techniques are often used to optimize integrated circuitdesigns or software programs to reduce power consumption, area and cost,or to increase performance such as operating frequency and/or datathroughput. Such matching techniques have been shown to be useful inseveral fields including high-level synthesis of digital logic andcompilers for software programs. Integrated circuits and otherelectronic systems include binary logic or other hardware structures toperform the functions that each circuit was designed to achieve.Likewise, compilers for software programs include data structures toperform the functions that the program was designed to achieve.

Generally, matching techniques are applied to either the structures orthe functions of integrated circuit designs and software programs.Structural matching techniques seek to identify separate structureswithin the design of an integrated circuit or software program and tocombine those structures, to the extent possible, into a singlestructure or subset of structures that perform the same overall functionas each of the separate structures individually or the same function asall structures together. Functional matching techniques, on the otherhand, seek to identify separate functions within the design of anintegrated circuit or a software program and combine those functionsinto a single function or subset of functions that perform the sameoverall function as each of the separate functions individually or thesame function as all structures together.

This combining of structures and/or functions may be referred to asresource sharing. FIG. 1 illustrates resource sharing among modules withidentical circuitry and/or functionality according to the prior art.FIG. 1 includes two identical circuits and/or functional modules, cloneA 101 and clone B 102, having the same I/O signals, IN₀ and OUT₀,respectively. Since clone A 101 and clone B 102 contain identicalcircuitry and/or functionality and the same I/O, clone A 101 and clone B102 are identified as candidates for sharing. Thus, clone A 101 andclone B 102 each includes identical circuitry and/or functionality thatmay be shared by both clone A 101 and clone B 102. This sharing ofresources among identical circuits and/or functions is achieved byreplacing clone A 101 and clone B 102 with a single shared resource 103and appropriately routing the common I/O. The structure and/orfunctionality of both clone A 101 and clone B 102 is maintained, but theresources required by the circuit are reduced through resource sharing.

Integrated circuit designs and/or software programs include variousstructures to perform various functions. These structures may includedifferent structures that perform different functions, similarstructures that perform identical functions, identical structures thatperform identical functions, and different structures that performidentical functions. Likewise, integrated circuit designs and/orsoftware programs may include identical functions implemented usingidentical structures, identical functions implemented using similar ordifferent structures, different functions implemented using similarstructures, and different functions implemented using differentstructures.

The goal of matching techniques is to identify structures and/orfunctionality in an integrated circuit design or software program thatcan be matched to enable resource sharing to the extent possible.However, previously known techniques are limited to either exactmatching or matching in terms of design descriptions, leaving somematches undetected. Conventional matching techniques have been limitedto either exact functional matching, or exact and approximate structuralmatching. For example, the 2008 publication by J. Cong and W. Jiangentitled “Pattern-based Behavior Synthesis for FPGA Resource Reduction,”Proc. ACM/SIGDA International Symposium on Field Programmable GateArrays (FPGA 2008) performs only structural matching techniques. TheCong publication finds bridging points of certain graphs to performstructural matching of integrated circuit hardware.

Several precursors of the Cong publication are also limited tostructural matching including the following: L. Pozzi, K. Atasu, P.Ienne, “Exact and Approximate Algorithms for the Extension of EmbeddedProcessor Instruction Sets,” IEEE Trans. on CAD 25(7), July 2006; X.Chen, D. L. Maskell, Y. Sun, “Fast Identification of Custom Instructionsfor Extensible Processors,” IEEE Trans. on CAD 26(2), February 2007; M.R. Corazao, M. Khalaf, L. Guerra, M. Potkonjak and J. M. Rabaey,“Performance Optimization Using Template Matching for Datapath-IntensiveHigh-Level Synthesis,” IEEE Trans. on CAD 15(8), August 1996, and A.Raghunathan and N. K. Jha, “SCALP: An Iterative-Improvement BasedLow-Power Data Path Synthesis System,” IEEE Trans. on CAD 16(11),November 1997.

In the category of functional matching, the recent publication by M.Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, E. Boutillon, entitled“Data-Flow Transformations using Taylor Expansion Diagrams,” Proc.ACM/IEEE Design Automation Conference (DAC) 2007, performs exactfunctional matching only. Likewise, the publication by P.Tummeltshammer, J. C. Hoe, M. Pueschel, entitled “Time-MultiplexedMultiple-Constant Multiplication,” IEEE TCAD 26(9), September 2007 isbased on exact functional matching. The Tummeltshammer publication isapplicable only to subsets of designs that perform multiplication bypre-determined constants, and only in the context of multiplicationcircuits. An earlier publication by P. Flores, J. Monteiro, E. Costa,entitled “An Exact Algorithm for the Maximal Sharing of Partial Terms inMultiple Constant Multiplications”, Proc. ACM/IEEE Int'l Conf. on CAD(ICCAD 2005) on sharing resources among multiplication circuits exhibitsthe same limitations as Ciesielski and Tummeltshammer. The publicationby A. Verma and P. Ienne entitled, “Improved use of the carry-saverepresentation for the synthesis of complex arithmetic circuits,” inProceedings of ICCAD 2007 discloses a representation of arithmeticcircuits that facilitates algorithms for exact functional matching.Similar techniques based on circuit transformations have been pursued inmore recent art, but generally share the same limitations.

In the case of functional matching, it is well-known that designs thatperform the same function, regardless of their internal structure, canbe functionally matched to enable resource sharing. In the case ofstructural mapping, identical or similar structures may be matchedwhether or not they perform identical functions.

Another line of prior art is motivated by techniques that have beenproposed for specialized physical layout of datapath circuits,exemplified by the U.S. Pat. No. 5,737,237 entitled “Method andapparatus for data path circuit layout design and memory medium forcausing computer to execute datapath design,” and U.S. Pat. No.6,560,761 entitled “Method of datapath cell placement for bitwise andnon-bitwise integrated circuits.” These techniques teach receiving asinput a datapath description for a datapath block and either prepare orreceive function macros in each of which there is a defined expansion toa circuit comprising a plurality of schematic leaf cells. Thesetechniques are commonly described for gate-level circuits.

In practice, datapath circuits can and often are extracted by designengineers. Since datapaths circuits (particularly adders andmultipliers) may admit compact and regular layout, attempts have beenmade at “regularity extraction,” often focusing on array-like structuresand repeated components. S. Hassoun and C. McCreary in their ICCAD 1999paper entitled, “Regularity extraction via clan-based structural circuitdecomposition,” points out that identifying repeating structuralregularities in circuits allows the minimization of synthesis,optimization and layout efforts. They term these repeated structures“templates” and cover the circuit with an appropriate set of templates.U.S. Pat. No. 6,148,433 entitled, “Systematic approach for regularityextraction,” also teaches generating a set of templates for a circuitthrough computer automated operations on a description of the circuit.The method includes covering the circuit with instances of a subset ofthe templates. Such templates may include adders, multipliers, andlarger configurations.

S. R. Arikati and R. Varadarajan in their ICCAD 1997 paper entitled, “Asignature based approach to regularity extraction,” computes numericalsignatures of circuit components and identifies similar components whendifferent signatures match. U.S. Pat. No. 6,557,159 entitled, “Methodfor preserving regularity during logic synthesis,” also determines agroup of elements in a circuit netlist having similar regularitysignatures. In this case, regularity is determined based on a physicallayout of the circuit. Further, this patent teaches determining aregularity signature for each element within the group and determiningwhether the regularity signatures for each element are identical.

U.S. Pat. No. 7,337,418 entitled, “Structural regularity extraction andfloorplanning in datapath circuits using vectors,” distinguishes afunctional regularity extraction component, a structural regularityextraction component, and a floorplanning component. Some embodiments ofthe functional regularity extraction component automatically generate aset of templates to cover a circuit. The templates generated by thefunctional regularity extraction component are used by a structuralregularity extraction component. While particularly noting regularity indatapath circuits and focusing on templates, this patent also teachesidentifying control logic for the logic design and excluding the controllogic from the set of vectors. A vector is a group of template instancesthat are identical in function and in structure. The techniquesdescribed in this patent are structural as they consider two subgraphsfunctionally equivalent, if and only if the following: (a) if they areisomorphic' (b) the logic functions of corresponding nodes are the same;and (c) the indices of corresponding edges are also the same. Under thiscriterion, the functional equivalence of (a+b)*c and (a*c+b*c), eventhough obvious to a person skilled in the art, cannot be established.While focusing on template covering and physical layout, the patent doesnot explain how one may identify control or data path.

SUMMARY OF THE DESCRIPTION

Embodiments described herein include a method and computer-readablemedium to perform a method, the method comprising locating one or moresubsets of an integrated an integrated circuit or software program withsimilar functionality and/or subsets with functionality similar to agiven template, assigning combinations of logic values to the controlinputs of the subsets to capture a plurality of co-factors performed bythe subsets for each of the combinations of logic values, and performingfunctional matching using the plurality of captured co-factors.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of at least certain embodiments of the inventioncan be obtained from the following detailed description in conjunctionwith the following drawings, in which:

FIG. 1 illustrates resource sharing among modules with identicalcircuitry and/or functionality according to the prior art.

FIG. 2A illustrates an implementation of a 4-input multiplexor circuit.

FIG. 2B illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a 4-inputmultiplexor according to an exemplary embodiment of the invention.

FIG. 2C illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a 4-inputmultiplexor according to an exemplary embodiment of the invention.

FIG. 2D illustrates an implementation of a 2-input binary decodercircuit.

FIG. 2E illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a 2-inputbinary decoder circuit according to an exemplary embodiment of theinvention.

FIG. 2F illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a 2-inputbinary decoder circuit according to an exemplary embodiment of theinvention

FIG. 3A illustrates an implementation of a 4-output demultiplexercircuit

FIG. 3B illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a4-output demultiplexer circuit according to an exemplary embodiment ofthe invention.

FIG. 3C illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a4-output demultiplexer circuit according to an exemplary embodiment ofthe invention.

FIG. 4A illustrates an implementation of a 1-bit full adder circuit.

FIG. 4B illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a 1-bitfull adder circuit according to an exemplary embodiment of theinvention.

FIG. 4C illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into input Cin of a 1-bitfull adder circuit according to an exemplary embodiment of theinvention.

FIG. 4D illustrates an implementation of a carry-ripple adder.

FIG. 5A illustrates a method for determining control inputs in anintegrated circuit design or software program according to an exemplaryembodiment of the invention.

FIG. 5B illustrates a method for determining control inputs in anintegrated circuit design or software program according to an exemplaryembodiment of the invention.

FIG. 6 illustrates a method of approximate functional matching accordingto an exemplary embodiment of the invention.

FIG. 7 illustrates an exemplary data processing system upon which themethods and apparatuses of the invention may be implemented.

DETAILED DESCRIPTION

Throughout the description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the present invention may be practicedwithout some of these specific details. In other instances, well-knownstructures and devices are shown in block diagram form to avoidobscuring the underlying principles of embodiments of the presentinvention.

A method and apparatus for approximate functional matching in electronicsystems is described. At least certain embodiments identify approximatefunctional matches not found by previously existing techniques. Theseembodiments simultaneously remove the restrictions of exact functionalmatching and structural matching taught in the prior art by matching oneor more subsets of an integrated circuit design or software program(hereinafter referred to collectively as “subsets”) to one or moretemplates, or by matching two or more subsets to each other. Someembodiments match subsets with different descriptions but very similarfunction, without requiring the function to be identical. This can bedone by analyzing a description of an integrated circuit design orsoftware program looking for subsets with similar function and/orsubsets whose function is similar to a given template. In both cases,the structural descriptions of the subsets may be unrelated, orunrelated to the structural descriptions of the given templates. Thematched subsets need not be exact (or identical to each other), but maydiffer in various respects.

Embodiments first consider one or more subsets of an integrated circuitdesign or software program with similar function and/or subsets whosefunction is similar to a given template. Embodiments then identifycontrol inputs in the subsets and/or templates, or read an alreadyprepared description identifying the control inputs. In the former case,embodiments evaluate the impact of assigning logic values to a giveninput. If this impact is deemed significant, the input is labeled as acontrol input (several criteria can be used to determine significantimpact, e.g., if some other inputs are made irrelevant or if the supportof some outputs changes significantly).

The identified control inputs are then used in certain embodiments tocapture a plurality of co-factors (or special-case functions). Byseparating the overall function of a subset into a plurality (such as anordered set or vector) of such co-factors, embodiments can leverageother functional matching techniques, including known techniques forexact functional matching. In at least certain embodiments, this processis referred to as approximate functional matching, since functionalmatching may be performed on matching candidates (subsets) with similar,but not exact functionality. If multiple or all co-factors match for twoor more subsets or for one or more subsets and a template, then anapproximate match is declared. An approximate match is also an exactmatch if for every control-input combination the co-factors match. Inthis way, embodiments can locate approximate functional matches notfound by prior art solutions. This can lead to a multitude of benefitsin various applications, including better utilization of availableresources, smaller chip size, smaller manufacturing cost, and smallerpower consumption.

I. First Criterion for Identifying Control Signals

In at least certain embodiments, control signals must be distinguishedfrom data signals. Word-level and Boolean decision diagrams can becombined to represent datapaths and control, using hybrid decisiondiagrams or by adding ROBDD-like multiplexor nodes to word-leveldecision diagrams. Either way, data must first be distinguished fromcontrol. Control signals generally appear in the middle of a circuitafter data comparisons, and can be clustered into multibit controlvalues. In one embodiment, inputs may be evaluated using two criteria.The first criterion is to perform constant propagation on a given inputto compare sets of internal signals made unobservable. That is, controlsignals may be identified by independently propagating binary values of0 and 1 through inputs of an integrated circuit or software program tosimplify the resulting netlist. If constant propagation of binary valuesof 0 and 1 substantially impacts the resulting circuit or program, thesignal may be considered control. However, there is no hard and fastrule as to what criteria may be used to determine whether an input isdata or control as several criteria may be used independently or incombination with each other including whether the input values activatevery different regions of the design, if other inputs are madeirrelevant by combinations of the input values, or if the support ofsome output changes substantially, to name a few. The determination ofcontrol signals may vary from implementation to implementation. What isdetermined to be control in one circuit or program may be determined tobe data in another. These judgments may be implementation specific basedon various factors including the type of circuit or program as well asindividualized needs of users and/or administrators.

For example, an explicit multiplexor is a well-known circuitconfiguration containing control circuitry. FIG. 2A illustrates animplementation of a 4-input multiplexor circuit. 4-input multiplexorcircuit 231 includes inputs In₀, In₁, In₂, In₃, En (enable), S₀, and S₁.The internal logic of 4-input multiplexor 231 is illustrated at thebottom portion of FIG. 2A including inverters 239-240, AND gates233-236, and OR gate 237. The equation represented by 4-inputmultiplexor 231 is as follows:

Out=En·[(In₀ S ₁ ′S ₀′) OR (In₁ S ₁ ′S ₀) OR (In₂ S ₁ S ₀′) OR (In₃ S ₁S ₀)]

Control inputs may be identified by determining the impact of theresulting netlist when constant propagation of the binary values of 0and 1 is applied to the inputs. FIG. 2B illustrates special-casecircuits (co-factors) resulting from propagating constant binary valuesof 0 and 1 into an input of a 4-input multiplexor according to anexemplary embodiment of the invention. In the illustrated embodiment,when S₁ is set=0, circuit 231 reduces to the simple AND-OR circuit shownat the top portion of FIG. 2B including only inverter 240, AND gates235-236, and OR gate 237. This can be seen by setting S₁=0 in the aboveequation resulting in the equation:

Out=En·[(In₀·1·S ₀′) OR (In₁·1·S ₀) OR (In₂·0·S ₀′) OR (In₃·0·S ₀)]

which simplifies to,

Out=En·[(In₀·1·S ₀′) OR (In₁·1·S ₀)].

With reference to the circuit elements of FIG. 2A, whenever input S₁ isset=0, the value 0 is propagated to inverter 239, and AND gates 235-236.Inverter 239 will always output a 1 when input S1 is set=0, thereforeinverter 239 is removed and a value of 1 is propagated to AND gates 233and 234. Whenever an AND function is applied to “anything” and the value1, the “anything” is propagated to the output. Since the output ofinverter 239 is equal to the value of 1, the AND gate 233 and 234 may besimplified into 3-input AND gates. The output of AND gate 233 willalways be the AND of inputs In₀, En, and S₀′. Therefore, the constantpropagation of the value of 0 at input S₁ results in reducing circuit231 as illustrated in the top portion of FIG. 2B. Likewise, the constantpropagation of the value of 1 at input S₁ results in reducing circuit231 as illustrated in the lower portion of FIG. 2B.

In at least certain embodiments, the impact of the applying the aboveconstant propagation on inputs of an integrated circuit or computerprogram is determined. If this impact is deemed significant enough, theinput is determined to be a control input. Otherwise, the input isdetermined to be data. In previous computer implemented methodologies,signals were always classified as either data or control signals with nooverlap. In contrast, embodiments provide a spectrum of signalclassifications with some signals being classified as definitely controlsignals, definitely data signals, or anywhere in-between. Inputs maythen be determined to be more control than data. Likewise, inputs may bedetermined to be more data than control. As discussed above, in someembodiments this determination may be made based on the impact ofconstant propagation of the binary values of 0 and 1 at inputs of anintegrated circuit or software program, and subsequently judging theimpact on the resulting circuit. Accordingly, embodiments envisionsignals that are almost determined to be data signals, but not quite.Likewise, embodiments envision signals that are almost determined to becontrol signal, but not quite.

In the illustrated embodiment of FIGS. 2A and 2B, it is clear thatapplying constant propagation to the input S₁ substantially reduces thecircuit 231. However, applying constant propagation to other inputs mayresult in only a minor or insubstantial impact on the resulting circuit231. FIG. 2C illustrates special-case circuits (co-factors) resultingfrom propagating constant binary values of 0 and 1 into an input of a4-input multiplexor according to an exemplary embodiment of theinvention. In the illustrated embodiment, whenever In₀ is set=0, circuit231 reduces slightly to the circuit illustrated at the top portion ofFIG. 2C including inverters 239-240, AND gates 234-236, and OR gate 237.Likewise, the constant propagation of the value of 1 at input In_(o)results in reducing circuit 231 as illustrated in the lower portion ofFIG. 2B.

In this case, applying constant propagation of binary values 0 and 1 toinput In₀ may be deemed (based on selected criteria discussed above) toreduce the logic of circuit 231 substantially less than applyingconstant propagation of binary values of 0 and 1 to input S₁. In atleast certain embodiments, the impact of performing the above constantpropagation on input S₁ may be deemed significant enough for S₁ to bedetermined to be a control signal rather than data, whereas the impactof performing constant propagation on input In₀ may be deemed tooinsubstantial for In₀ to be determined to be a control signal. However,as discussed above, different impacts on a particular circuit may bejudged differently depending on any number of criteria discussed aboveincluding whether the input values activate very different regions ofthe design, if other inputs are made irrelevant by combinations of theinput values, or if the support of some output changes substantially.

Another example is demonstrated in FIGS. 2D-2F. FIG. 2D illustrates animplementation of a 2-input binary decoder circuit. 2-input decoder 201includes inputs In₀, In₁, En (enable) and outputs Out₀, Out₁, Out₂ andOut₃. The internal logic of 2-input decoder 201 is illustrated in thelower portion of FIG. 2D including inverters 219-220, and AND gates211-214. The equations represented by 2-input decoder 201 are asfollows:

Out₀=In₁′·In₀ ′·En

Out₁=In₁′·In₀ ·En

Out₂=In₁·In₀ ′·En

Out₃=In₁·In₀ ·En

In certain embodiments, control inputs may be identified by determiningthe impact of the resulting netlist when inputs are constant propagatedwith the binary values of 0 and 1. FIG. 2E illustrates special-casecircuits (co-factors) resulting from propagating constant binary valuesof 0 and 1 into an input of a 2-input binary decoder circuit accordingto an exemplary embodiment of the invention. In the illustratedembodiment, whenever In₀ is set=0, circuit 201 reduces to the simple ANDcircuit shown at the top portion of FIG. 2E including only inverter 220,and AND gates 211 and 213. This can be seen by setting In₀ to 0 in theabove equation resulting in the following equations:

Out₀=In₁′·1·En

Out₁=In₁′·0·En

Out₂=In₁·1·En

Out₃=In₁·0·En

which simplifies to,

Out₀=In₁ ′·En

Out₁=0

Out₂=In₁ ·En

Out₃=0

Likewise, the constant propagation of the value of 1 at input In₀results in reducing circuit 201 as illustrated in the lower portion ofFIG. 2E. In the illustrated embodiment of FIGS. 2D and 2E, it is notnecessarily unambiguous that applying constant propagation to the inputIn₀ substantially reduces the circuit 201. However, applying constantpropagation to other inputs may result in a substantial impact on theresulting circuit 201. FIG. 2F illustrates special-case circuits(co-factors) resulting from propagating constant binary values of 0 and1 into an input of a 2-input binary decoder circuit according to anexemplary embodiment of the invention. In the illustrated embodiment,whenever En is set=1, circuit 201 reduces slightly to the circuitillustrated at the top portion of FIG. 2F including inverters 219-220and AND gates 212 and 214. Thus, the impact of propagating the constantbinary value of 1 to input En may be deemed insubstantial based on thisresult. In contrast, the constant propagation of the value of 1 at inputEn may be deemed to be substantial since it results in reducing circuit201 as illustrated in the lower portion of FIG. 2F. In at least certainembodiments, therefore, input En may be determined to be a controlsignal rather than data based on the criteria discussed above sinceapplying constant propagation of binary values 0 and 1 to input Enreduces the logic of circuit 201 substantially more than applyingconstant propagation of values of 0 and 1 to input In₀. As a result, theimpact of performing the above constant propagation on input En may bedeemed significant enough for En to be labeled as a control signalrather than data, whereas the impact of performing constant propagationon input In₀ may be deemed too insubstantial for In₀ to be determined tobe a control signal.

II. Second Criterion for Identifying Control Signals

Sometimes control inputs may not be determined based on the embodimentsdescribed above. In such cases, embodiments describe a second criterionwhich may be used to distinguish control signals form data signals. Thesecond criterion is not mutually exclusive from the first criteriondiscussed above. The two criteria may either be performed independentlyand/or in conjunction with each other. An example of using the secondcriterion in conjunction with the first criterion is demonstrated inFIGS. 3A-3C. FIG. 3A illustrates an implementation of a 4-outputdemultiplexor circuit. 4-output demultiplexer 301 includes inputs S₀,and S₁, In, and outputs Out₀, Out₁, Out₂ and Out₃. The internal logic of4-output demultiplexor 301 is illustrated in the lower portion of FIG.3A including inverters 339-340 and AND gates 333-336. The equationsrepresented by 4-output demultiplexor 201 are as follows:

Out₀ =S ₁ ′·S ₀′·IN

Out=S ₁ ′·S ₀·IN

Out₂ =S ₁ ·S ₀′·IN

Out₃ =S ₁ ·S ₀·IN

In certain embodiments, control inputs may not be identified bydetermining the impact of the resulting netlist when inputs are constantpropagated with the binary values of 0 and 1. In this case, the firstcriterion may not correctly identify control inputs. FIG. 3B illustratesspecial-case circuits (co-factors) resulting from propagating constantbinary values of 0 and 1 into an input of a 4-output demultiplexercircuit according to an exemplary embodiment of the invention. In theillustrated embodiment, whenever input IN is set=0, circuit 301 reducesto a simple ground (GND) circuit with all outputs tied to voltage ground(binary 0). This can be seen by setting In=0 in the above equationresulting in the following equations:

Out₀ =S ₁ ′·S ₀′·0

Out₁ =S ₁ ′·S ₀·0

Out₂ =S ₁ ·S ₀′·0

Out₃ =S ₁ ·S ₀·0

which simplifies to,

Out₀=0

Out₁=0

Out₂=0

Out₃=0

Likewise, the constant propagation of the value of 1 at input IN resultsin reducing circuit 301 as illustrated in the lower portion of FIG. 3B.In the illustrated embodiment of FIGS. 3B, the impact of applyingconstant propagation of the values of 0 and 1 to input IN may beconsidered ambiguous. In the top portion of FIG. 3B, setting IN=0substantially simplifies the circuit 301, whereas in the lower portionof FIG. 3B, setting IN=1 hardly changes circuit 301 at all.

FIG. 3C illustrates special-case circuits (co-factors) resulting frompropagating constant binary values of 0 and 1 into an input of a4-output demultiplexer circuit according to an exemplary embodiment ofthe invention. In the illustrated embodiment, whenever input S₁ isset=0, circuit 301 is reduced to the circuit shown in the top portion ofFIG. 3C. Likewise, the constant propagation of the value of 1 at inputS₁ results in reducing circuit 301 as illustrated in the lower portionof FIG. 3C. In the illustrated embodiment of FIGS. 3C, the impact ofapplying constant propagation of the values of 0 and 1 to input S₁ maybe considered ambiguous. This is because propagating the constant binaryvalues of 0 and 1 to input S₁ reduces circuit 301 somewhat. In at leastcertain embodiments, this impact may be deemed too insubstantial to beconsidered a control input.

In these cases, the first criterion may not correctly identify controlinputs and the second criterion may be used. The second criteriondetermines the number of bit-signals controllable by a given inputsignal. That is, the second criterion determines the amount of outputsthat are sensitized by a given input. An input sensitizes a given outputwhenever a logic transition at the input produces a logic transition atthe given output for various configurations of side-inputs. To checkeach downstream signal, an SAT-based Boolean-difference computation orATPG-style justification can be used. For example, referring back toFIG. 3A, the second criterion is applied to inputs X and S₁. When thesecond criterion is applied to input X, the side-inputs will be S₁ andS₀. The second criterion determines how many outputs are sensitized by atransition in X for given values of S₁ and S₀. The following tablesummarizes the results of a logic transition in X for each combinationof values of S₁ and S₀:

Outputs Assigned Assigned Sensitized by Values of S₁ Values of S₀transition of X 0 0 Out₀ 0 1 Out₁ 1 0 Out₂ 1 1 Out₃Table 1.1 illustrates various outputs sensitized by input X.

A transition in the logic value of X for each combination of S₁ and S₀sensitizes at most only one (1) output as indicated by table 1.1 above.In at least certain embodiments, sensitizing only one output may not beconsidered significant enough to label X as a control signal. In such acase, the input X may be considered to be a data signal rather than acontrol signal.

When the second criterion is applied to input S₁, on the other hand, theside-inputs will be X and S₀. The second criterion determines how manyoutputs are sensitized by a transition in S₁ for given values of X andS0. The following table summarizes the results of a logic transition inS₁ for each combination of values of X and S₀:

Outputs Assigned Assigned Sensitized by Values of S₀ Values of Xtransition of S₁ 0 0 None 0 1 Out₀, Out₂ 1 0 None 1 1 Out₁, Out₃Table 2.2 illustrates various outputs sensitized by input S₁.A transition in the logic value of S₁ for each combination of X and S₀sensitizes as many as two (2) outputs as indicated by table 1.2 above.This is half of the total outputs in circuit 301, and in at leastcertain embodiments, sensitizing half of the outputs in a particularcircuit may be considered significant enough to label S₁ as a controlsignal. As discussed above, however, there is no hard-and-fast rule, andwhether a signal is determined to be control or data may vary from caseto case.

In this manner, the second criterion may identify control signals notidentified using the first criterion alone. This is particularly usefulfor identifying demultiplexors (such as circuit 301) and add/subtractcontrol lines of adders/subtractors.

Other times ambiguous findings may result using both of the abovemethods. FIG. 4A illustrates an implementation of a 1-bit full addercircuit. 1-bit adder 401 includes inputs A, B and Cin, and outputs Coutand S (sum). The internal logic gates of 1-bit adder 301 are shown inthe bottom portion of FIG. 4A including exclusive-OR (XOR) gates411-412, AND-gates 413-414, and OR-gate 415. The equations representedby 1-bit adder 401 are as follows:

S=(A XOR B) XOR Cin

Cout=(A·B) OR (Cin·(A XOR B))

In these embodiments, however, control inputs may not be properlyidentified by determining the impact of the resulting netlist wheninputs are constant propagated with the binary values of 0 and 1.Additionally, control inputs may not be properly identified bydetermining how many outputs are sensitized by a given input. FIG. 4Billustrates special-case circuits (co-factors) resulting from applyingconstant propagation of binary values 0 and 1 to an input of a 1-bitfull adder circuit according to an exemplary embodiment of theinvention. In the illustrated embodiment, when input A is set to 0,circuit 401 reduces to the half-adder circuit shown in the top portionof FIG. 4B including only XOR gate 412 and AND gate 413. The logicfunctions of XOR gate 411, AND gate 414, and OR gate 415 have beenresolved by propagating the value 0 of input A. This can be seen bysetting A=0 in the above equation resulting in the following equations:

S=(0 XOR B) XOR Cin

Cout=(0·B) OR (Cin·(0 XOR B))

which simplifies to,

S=B XOR Cin

Cout=Cin·B

This can also be seen by referring back to FIG. 4A. Whenever input A isset=0, the inputs of XOR 411 are 0 and B. Whenever the value of a firstinput to an XOR gate is=0, the output value will be equal to the valueof the other input(s) to the XOR gate, in this case B. So, input Bpropagates through to the input of XOR 412. XOR 411 is removed.Likewise, when input A is set=0, the inputs of AND 414 are 0 and B.Thus, 0 propagates through to the input of OR gate 415, and AND gate 414is removed. Now the inputs to OR gate 415 are the output of AND 413 and0. Whenever a first input to a 2-input OR gate is a 0, then the outputwill be equal to the value of the other input(s). In this case theoutput of AND 413 is the other input of OR gate 415 and, therefore, theoutput of AND 413 propagates through to Cout. OR gate 415 is removed.The resulting circuit is shown in the top portion of FIG. 4B. Similarly,when input A is set=1, circuit 401 reduces to the circuit shown in thebottom portion of FIG. 4B including only XOR gate 412, AND gate 413,inverter 417 and OR gate 415. It is noted that XOR 211 reduces toinverter 417. The logic functions of XOR gate 411 and AND gate 414 havebeen resolved by propagating the value 1 into input A.

Similarly, FIG. 4C illustrates special-case circuits (co-factors)resulting from applying constant propagation of binary values 0 and 1 toinput Cin of a 1-bit full adder circuit according to an exemplaryembodiment of the invention. In the illustrated embodiment, when inputCin is set=0, circuit 401 reduces to the half-adder circuit shown in thetop portion of FIG. 4C including only XOR gate 411 and AND gate 414. Thelogic functions of XOR gate 412, AND gate 413, and OR gate 415 have beenresolved by propagating the value 0 of input Cin. When input Cin isset=1, circuit 401 reduces to the circuit shown in the bottom portion ofFIG. 4B including only XOR gate 412, AND gate 413, inverter 417 and ORgate 415. It is noted that XOR 411 reduces to inverter 417. The logicfunctions of XOR gate 411 and AND gate 414 have been resolved bypropagating the value 1 of input A.

In the case of 1-bit full adder circuit 401, the impact of propagatingconstant values of 0 and 1 into inputs A and Cin may be considered tohave yielded ambiguous results. Performing constant propagation oninputs A and Cin both yielded reduced circuits with the same number ofgates in both cases. This being the case, a decision as to whether eachinput A and Cin should be considered control or data may be tough todetermine. In at least certain embodiments, this may be resolved byevaluating the inputs A and Cin using the second criterion ofdetermining how many outputs are sensitized by a given input may beperformed. However, the second criterion also may be considered to yieldambiguous results. For example, referring again to FIG. 4A, wheneverinput A of 1-bit full adder 401 is in a logic transition for variouscombinations of B and Cin, outputs S and Cout are both sensitized.Likewise, whenever input Cin is in a logic transition for variouscombinations of A and B, outputs S and Cout are also both sensitized.

Thus, under both the first and second criterion, the results may beconsidered ambiguous depending on the particular implementation of the1-bit full adder 401. In such a case, it may be difficult to determineif inputs A and Cin are control signals or data. However, both A and Cinmay sensitize fewer or more outputs in a chain of 1-bit full addercircuits. Typically, 1-bit adders are configured in combination withother 1-bit adders in order to perform multi-bit additions and/orsubtractions. FIG. 4D illustrates an implementation of a carry-rippleadder. Adder modules can be implemented in several ways, which differ instructure, cost and speed (delay). A “carry-ripple” adder module is amultilevel network formed by the connection of 1-bit adders, called“full-adders”, as illustrated in FIG. 4D. The full-adder modules performaddition of a pair of input bits (such as inputs A and B) and a carryinput (such as input Cin), producing a sum bit (S) and a carry output(Cout). That is, the inputs to full-adder i are bits A_(i) and B_(i)from the input vector, and a carry input, Cin_(i) coming from full-adderi−1. As output, full-adder i produces the sum bit S_(i) and thecarry-out bit Cout_(i+1) (which is connected as carry input tofull-adder i+1).

In the illustrated embodiment, it is clear that the carry-in input Cinsensitizes substantially more outputs along the carry chain than theinputs A or B to any one of the full-adders. Thus, although looking atthe 1-bit adder configuration standing alone, it may be ambiguouswhether inputs A, B and Cin represent data or control. However, whenconsidering a multilevel implementation, such as the carry-ripple adderof FIG. 4D formed by the chain of 1-bit full adders 401, it may becomeclear that Cin is more closely akin to a control input than a data inputbased on the total number of outputs sensitized by the carry chain. Italso may become clear that inputs A and B are more closely akin to datainputs rather than control based on the number of outputs sensitized bythe inputs A and B. Accordingly, in at least certain embodiments, inputCin may be identified as a control signal by viewing the input in lightof the entire multilevel implementation of the 1-bit full-adder circuitusing the second criterion. Likewise, inputs A and B may be identifiedas data signals by viewing the inputs in light of the entire multilevelimplementation of the 1-bit full-adder circuit using the secondcriterion.

A method for determining control inputs in an integrated circuit designor software program according to an exemplary embodiment of theinvention is illustrated in FIG. 5A. The method begins by consideringvarious candidates for matching in an integrated circuit design orsoftware program (operation 501). This can be done in at least certainembodiments by searching for and locating subsets with similar functionand/or subsets whose function is similar to a given template. In bothcases, structural descriptions of the subsets may be unrelated, orunrelated to the structural descriptions of the given templates.Constant binary values of 0 and 1 are then propagated into the inputs ofthe identified candidates (operation 505) and the impact of the constantpropagation is determined and the input is ranked with respect to otherinputs (operation 507). In the illustrated embodiment, control flows todecision block 509 where it is determined whether the impact of theconstant propagation is substantial enough to label the input as acontrol signal. As discussed previously, whether the impact of constantpropagation is substantial may be relative to the particular case asimplementations vary widely. If the impact of the constant propagationis considered substantial, the input is determined to be control(operation 511) and control flows to FIG. 6. If the impact of theconstant propagation is not considered substantial, the potential arisesthat the input could be classified as data (operation 513) and controlflows to FIG. 5B where the second criterion is applied to the input.

FIG. 5B illustrates a method for determining control inputs in anintegrated circuit design or software program according to an exemplaryembodiment of the invention. In certain cases, control signals may notproperly be identified using the first criterion (method in FIG. 5A),and so, the second criterion may be applied. The number of outputssensitized by a logic transition of an input in question is firstdetermined (operation 515) and ranked (operation 517). For eachcombination of side-inputs, the number of outputs sensitized (i.e.,potentially making a logic transition) for each combination ofside-inputs is determined. If this number is considered substantial(operation 519), the input may determined to be a control input(operation 521). If this number of sensitized outputs is determined tobe insubstantial, then the input may be determined to be data (operation523). This completes the method of FIGS. 5A-5B.

III. Approximate Functional Matching

With control inputs known and ranked, various combinations of thecontrol inputs may be applied to the identified control signals toreduce the integrated circuit or software program to a subset that canbe matched to templates and/or other subsets using known matchingtechniques. Using the control rankings, a small subset of controlsignals is found and all possible combinations of the subset of controlsignals is considered. A series of co-factors may then be captured bytoggling combinations of values of the control inputs. Specifically, fora known control input set, the function performed by the circuit orsoftware program may be captured by assigning various combinations oflogic values to the control inputs. Each combination of control inputsassigned may reduce the circuit or software program. For eachcombination, the reduced circuit or software program is captured as aco-factor (special-case function), which may be represented as aplurality (ordered set or vector) of co-factors, each corresponding to aparticular combination of values assigned to the control inputs.

Thus, in embodiments, control inputs are first identified using thefirst criterion and/or the second criterion discussed above, then theco-factors of a circuit or program are captured by assigning variouscombinations of these control inputs. The co-factors may then be matchedusing known functional matching techniques. For example, assuming thatthe signals S₁ and S₀ are identified as control signals in FIG. 2A, thenassigning various logic values to these control inputs yields a numberof co-factors which can then be matched using existing techniques. Theequation given above describing circuit 231 is as follows:

Out=En·[(In₀ S ₁ ′S ₀′) or (In₁ S ₁ ′S ₀) or (In₂ S ₁ S ₀′) or (In₃ S ₁S ₀)],

When combinations of control inputs are assigned to the values of S₁ andS₀, the following co-factors result:

Assigned Values of S₁ Assigned Values of S₀ Captured co-factors 0 0 Out= En · In₀ 0 1 Out = En · In₁ 1 0 Out = En · In₂ 1 1 Out = En · In₃

Each of the co-factors in the above case reduces circuit 231 of FIG. 2Adown to a single AND gate structure each with the common input driven byinput En. These simple enable-driven AND gate structures then becomecandidates for matching, and may subsequently be matched to one or moretemplates, or one or more other candidates for matching so identified inan integrated circuit design or software program.

This matching may be performed using any known functional matchingtechniques. Some embodiments match subsets with different descriptionsbut very similar function without requiring the function to beidentical. Thus, approximate functional matching may be performed on oneor more identified matching candidates according to the principlesoutlined in this description. These identified matching candidates maythen be evaluated and possibly ranked based on overall resource savingsthey could provide to the circuit or program.

FIG. 6 illustrates a method of performing approximated functionalmatching according to an exemplary embodiment of the invention. Asdiscussed above, combinations of values of the identified control inputsare assigned (operation 601) and co-factors are captured for each of theassigned combinations (operation 603). Then functional matches are foundamong the co-factors using known matching techniques (operation 605).These techniques may be used with integrated circuits and softwareprograms. For example, a subset of the software program can be afunction (using C++ syntax) such as:

  int max (int a, int b)   {    return (a>b ? a : b);   } Or   doublemax (double a, double b)   {    return (a>b ? a : b);   }For these simple programs, a “control input” would be the type used (ora collection of types). A super-function that explicitly exposes thetype as a parameter would be as follows:

template<class T> T max (T a, T b) {  return (a>b ? a : b); }Not only functions, but also fragments of functions can be eligiblesubsets. For example:

for (int i=0; i++; i<N) { c[i]=a[i]+gamma*b[i]; }would match

for (int j=0; j++; j<M) {  z[i] =x[i] +delta*y[i]; }

Once the matching candidates are identified, known matching techniquesmay be applied. One technique is to conglomerate adjacent matches intoclusters to reduce multiplexing overhead. For example, for the subsetsrepresented by the equations (A+B)*C and (X+Y)*Z, the adders and themultipliers would be identified as matching candidates (even though theinputs are different). If each of the subsets is multiplexed ontoitself, then two (2) multiplexors and two (2) demultiplexors would berequired. However, if the matches are conglomerated into anadder-multiplier supermodule, then only one (1) multiplexor is required.

Another matching technique is to match functional equivalents withdifferent internal structure. For example, the subsets represented bythe equations (A+B*C) and (A*C+B*C) are functionally equivalent and maybe matched as so even though they have different structure. Similarly,structural equivalence can often be relaxed by several gates which canthen be multiplexed. For example, an unmatched inverter can be turnedinto an XOR gate controlled by an identified control input such as athread id.

Moreover, different modules can be generalized into a configurablesupermodule of approximately the same size, e.g., addition, subtractionand less-than comparisons can be performed by one supermodule with two(2) select lines. Instead of using a separate adder and subtractor inthis example, a standard adder-subtractor may be used with aconfiguration bit. Consider building an adder-subtractor from an adderand a subtractor. Once a 4-bit adder-subtractor is built by approximatefunctional matching, it is known that its add-or-subtract configurationbit is control, and everything else is data. So, when approximatefunctional matching is performed bit-by-bit, the two cases of “add” and“subtract” are considered with two new data bits which can be used forco-factoring. This gives three control signals and eight cofactors.Since all cofactors must match, one additional bit of the result can becomputed by finding only several gates.

If many pairs of co-factors match, they can be multiplexed to build up asupermodule that can act as a constituent component to be matched withother supermodules (depending on select bits). The supermodule may thenbe optimized. For example, the expressions (sel ? A+B:A−B) and (sel ?A−B:A+B) can be viewed as multiplexors selecting between values of A+Band A−B computed by an adder and a subtractor. But, they do not matchexactly because they differ by an inverter on the select bit. This canbe remedied using a supermodule with an XOR gate replacing the invertercontrolled by thread_id (0 or 1). For thread_id 0, the circuit can bemodeled by a wire, and for thread_id 1, the circuit is modeled as aninverter. This can be generalized by considering the multiplexerfunctional modules (x ? a:b) and (x ? b:a) as approximate matches, andtheir supermodule f(a, b, x, sel) can be simplified to (x XOR sel ?a:b).

A second method can be illustrated by the equivalence (sel ? a+b:a)˜(a+b& sel). This function is a ternary operator meaning, if (sel) thenreturn a+b, else return a. This can be approximated by the expression(a+b & sel) as follows:

if sel==0, then b & sel=0, and a+b & sel=a

Generally, for small enough co-factors, say C0 and C1, approximatefunctional matching is performed by synthesizing the function f(x, sel)=C_(sel)(x) for every sel=0, 1. Consider two cases for sel==0 and sel==1as follows:

f(x, 0)=C0(x) and f(x, 1)=C1(x).

So, f(x, sel) functionally multiplexes C0 and C1 onto the same function.In other words, f(x, sel)=(sel ? C0(x):C1(x)), which is the expressionabove.

To find supermodules for multiple-output circuits or software,especially arithmetics, the outputs may be ordered by the size of theirsupport (inputs). Then the inputs may be ordered based on how many (andwhich) outputs they control. At least certain embodiments may thenperform approximate functional matching on a few (k=4) least significantbits (LSBs). The LSBs of each of the matching candidates may be viewedas control signals and the approximate functional matching is performedas before by toggling the combinations of control inputs yieldingvarious co-factors which may then be matched. If an acceptablesupermodule is found, it may be extended in the above fashion by takingone or more LSBs of the supermodule and once again viewing these bits ascontrol. This iteration may be performed until all inputs have beenconsidered. However, this is given by way of illustration and notlimitation as any number of inputs may be considered within the scope ofthis description. At each iteration, control signals are both selectbit(s) of the supermodule, and the next bit(s) in the ordering. Newlogic (often 1-3 gates) can be found by exhaustive search or bytransduction.

A particular extension of this method allows the processing of a largenumber of subsets and/or templates without considering all pairs. Thisis accomplished by using a hash function of the co-factors so as tocharacterize each subset by a vector of numbers. One way to performhashing of the co-factors is to serialize their representations.Co-factors may be converted into character strings or bit-strings, andthen the strings may be hashed using standard techniques. In at leastcertain embodiments, the vectors can then be subjected to another hashfunction referred to as a “locality-sensitive hash function” to arriveat a single number such that similar vectors produce similar numbers.Basically, we hash certain hash values of the co-factors, usingdifferent hash functions. Then, subsets and templates that would formapproximate matches are likely to produce the same final numbers (i.e.,hash into the same bucket so to speak), which allows matching co-factorsto be identified efficiently without having to consider all pairs.

For example, if there are 16 co-factors and 32 co-factors, thenconsidering all pairs would require 16*32 operations. Instead, the hashfunctions of the 16 and 32 co-factors may be computed and the resulting48 values sorted into sets. This puts equal values next to each other,so that only co-factors with equal hash values are considered. If thereare no equal hash values, then there will be no matches in thisembodiment.

In some embodiments, a functional matching criterion can be evaluated byconnecting two subsets via multiplexors and then performing knownoptimizations, i.e. resource sharing, factoring, constant propagation,merging equivalent selector/multiplexor inputs. The result can then beevaluated on a number of criteria such as area, timing, power relativeto the same criteria for the original subsets to form a functionalmatching criterion.

Further, the multiplexed subsets can be converted to various functionalforms for Boolean or arithmetic functions, followed by comparingcharacteristics of the forms such as number of nodes in graph basedfunctional forms.

Pairs of co-factors can also be compared by connecting them via selectlogic and applying optimizations. The result can then be compared to theoriginal co-factors on a variety of criteria. Again, this comparison canbe based on converting the result to a functional form and measuringproperties of the functional form relative to the properties of thefunctional forms of the co-factors.

In some embodiments, supermodules are constructed by connecting subsetsvia select logic and then performing optimizations to reduce thetargeted criteria. If the resulting supermodule is similar in cost tothe original subsets then it can potentially replace the originalsubsets at a savings.

Another extension of the invention is to use parametric matches andclosely-related operations when capturing co-factors, such as matchingan 8-bit multiplier to a 10-bit multiplier (because the latter can alsoimplement the former) or matching an 8-bit adder to a 10-bit subtractor(for the same reason). In such cases, the more general component isconsidered.

In this manner, a method and apparatus for approximate functionalmatching in electronic systems is described. At least certainembodiments identify approximate functional matches not found bypreviously existing techniques. These embodiments simultaneously removethe restrictions of exact functional matching and structural matchingtaught in the prior art by matching one or more subsets of an integratedcircuit design or software program (hereinafter referred to collectivelyas “subsets”) to one or more templates, or by matching two or moresubsets to each other. Some embodiments match subsets with differentdescriptions but very similar function, without requiring the functionto be identical. By separating the overall function of a subset into aplurality (such as an ordered set or vector) of such co-factors,embodiments can leverage other functional matching techniques, includingknown techniques for exact functional matching. In at least certainembodiments, this process is referred to as approximate functionalmatching, since functional matching may be performed on matchingcandidates (subsets) with similar, but not exact functionality. Ifmultiple or all co-factors match for two or more subsets or for one ormore subsets and a template, then an approximate match is declared. Thiscan lead to a multitude of benefits in various applications, includingbetter utilization of available resources, smaller chip size, smallermanufacturing cost, and smaller power consumption.

In at least certain embodiments, the foregoing methods and apparatusesdescribed herein may be used in conjunction with any data processingsystem. FIG. 7 shows one example of a typical data processing system,such as data processing system 700, which may be used with the presentinvention. Note that while FIG. 7 illustrates various components of adata processing system, it is not intended to represent any particulararchitecture or manner of interconnecting the components as such detailsare not germane to the present invention. It will also be appreciatedthat network computers and other data processing systems which havefewer components or perhaps more components may also be used. The dataprocessing system of FIG. 7 may, for example, be a workstation, or apersonal computer (PC) running a Windows operating system, or an AppleMacintosh computer.

As shown in FIG. 7, the data processing system 701 includes a system bus702 which is coupled to a microprocessor 703, a ROM 707, a volatile RAM705, and a non-volatile memory 706. The microprocessor 703, which may bea processor designed to execute any instruction set, is coupled to cachememory 704 as shown in the example of FIG. 7. The system bus 702interconnects these various components together and also interconnectscomponents 703, 707, 705, and 706 to a display controller and displaydevice 708, and to peripheral devices such as input/output (I/O) devices710, such as keyboards, modems, network interfaces, printers, scanners,video cameras and other devices which are well known in the art.Typically, the I/O devices 710 are coupled to the system bus 702 throughinput/output controllers 709. The volatile RAM 705 is typicallyimplemented as dynamic RAM (DRAM) which requires power continually inorder to refresh or maintain the data in the memory. The non-volatilememory 706 is typically a magnetic hard drive or a magnetic opticaldrive or an optical drive or a DVD RAM or other type of memory systemswhich maintain data even after power is removed from the system.Typically, the non-volatile memory 706 will also be a random accessmemory although this is not required. While FIG. 7 shows that thenon-volatile memory 706 is a local device coupled directly to the restof the components in the data processing system, it will be appreciatedthat the present invention may utilize a non-volatile memory which isremote from the system, such as a network storage device which iscoupled to the data processing system through a network interface suchas a modem or Ethernet interface (not shown). The system bus 702 mayinclude one or more buses connected to each other through variousbridges, controllers and/or adapters (not shown) as is well known in theart. In one embodiment the I/O controller 709 includes a USB (UniversalSerial Bus) adapter for controlling USB peripherals, and/or an IEEE-1394bus adapter for controlling IEEE-1394 peripherals.

It will be apparent from this description that aspects of the presentinvention may be embodied, at least in part, in software, hardware,firmware, or in combination thereof. That is, the techniques may becarried out in a computer system or other data processing system inresponse to its processor, such as a microprocessor, executing sequencesof instructions contained in a memory, such as ROM 707, volatile RAM705, non-volatile memory 706, cache 704 or a remote storage device (notshown). In various embodiments, hardwired circuitry may be used incombination with software instructions to implement the presentinvention. Thus, the techniques are not limited to any specificcombination of hardware circuitry and software or to any particularsource for the instructions executed by the data processing system 700.In addition, throughout this description, various functions andoperations are described as being performed by or caused by softwarecode to simplify description. However, those skilled in the art willrecognize that what is meant by such expressions is that the functionsresult from execution of code by a processor, such as the microprocessor703.

A machine readable medium can be used to store software and data whichwhen executed by the data processing system 700 causes the system toperform various methods of the present invention. This executablesoftware and data may be stored in various places including for exampleROM 707, volatile RAM 705, non-volatile memory 706, and/or cache 704 asshown in FIG. 7. Portions of this software and/or data may be stored inany one of these storage devices.

The invention also relates to apparatus for performing the operationsherein. This apparatus may be specially constructed for the requiredpurposes, or it may comprise a general purpose computer selectivelyactivated or reconfigured by a computer program stored in the computer.Such a computer program may be stored or transmitted in amachine-readable medium. A machine readable medium includes anymechanism that provides (i.e., stores and/or transmits) information in aform accessible by a machine (e.g., a computer, network device, personaldigital assistant, manufacturing tool, any device with a set of one ormore processors, etc.). For example, a machine readable medium includesrecordable/non-recordable media such as, but not limited to, amachine-readable storage medium (e.g., any type of disk including floppydisks, optical disks, CD-ROMs, and magnetic-optical disks, read-onlymemories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flashmemory, magnetic or optical cards, or any type of media suitable forstoring electronic instructions), or a machine-readable transmissionmedium such as, but not limited to, any type of electrical, optical,acoustical or other form of propagated signals (e.g., carrier waves,infrared signals, digital signals, etc.).

Additionally, it will be understood that the various embodimentsdescribed herein may be implemented with data processing systems whichhave more or fewer components than system 1600; for example, such dataprocessing systems may be a cellular telephone or a personal digitalassistant (PDA) or an entertainment system or a media player (e.g., aniPod) or a consumer electronic device, etc., each of which can be usedto implement one or more of the embodiments of the invention.

Throughout the foregoing specification, references to “one embodiment,”“an embodiment,” “an example embodiment,” etc., indicate that theembodiment described may include a particular feature, structure, orcharacteristic, but every embodiment may not necessarily include theparticular feature, structure, or characteristic. Moreover, such phrasesare not necessarily referring to the same embodiment. When a particularfeature, structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to bring about such a feature, structure, orcharacteristic in connection with other embodiments whether or notexplicitly described. Various changes may be made in the structure andembodiments shown herein without departing from the principles of theinvention. Further, features of the embodiments shown in various figuresmay be employed in combination with embodiments shown in other figures.

In the description as set forth above and claims, the terms “coupled”and “connected,” along with their derivatives, may be used. It should beunderstood that these terms are not intended to be synonymous with eachother. Rather, in particular embodiments, “connected” is used toindicate that two or more elements are in direct physical or electricalcontact with each other. “Coupled” may mean that two or more elementsare in direct physical or electrical contact. However, “coupled” mayalso mean that two or more elements are not in direct contact with eachother, but yet still co-operate or interact with each other.

Some portions of the detailed description as set forth above arepresented in terms of algorithms and symbolic representations ofoperations on data bits within a computer memory. These algorithmicdescriptions and representations are the means used by those skilled inthe data processing arts to most effectively convey the substance oftheir work to others skilled in the art. An algorithm is here, andgenerally, conceived to be a self-consistent sequence of operationsleading to a desired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, transferred, combined, compared, and otherwisemanipulated. It has proven convenient at times, principally for reasonsof common usage, to refer to these signals as bits, values, elements,symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the discussion as setforth above, it is appreciated that throughout the description,discussions utilizing terms such as “processing” or “computing” or“calculating” or “determining” or “displaying” or the like, refer to theaction and processes of a computer system, or similar electroniccomputing device, that manipulates and transforms data represented asphysical (electronic) quantities within the computer system's registersand memories into other data similarly represented as physicalquantities within the computer system memories or registers or othersuch information storage, transmission or display devices.

The invention also relates to apparatus for performing the operationsherein. This apparatus may be specially constructed for the requiredpurposes, or it may comprise a general purpose computer selectivelyactivated or reconfigured by a computer program stored in the computer.Such a computer program may be stored or transmitted in amachine-readable medium, such as, but is not limited to, amachine-readable storage medium (e.g., any type of disk including floppydisks, optical disks, CD-ROMs, and magnetic-optical disks, read-onlymemories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flashmemory, magnetic or optical cards, or any type of media suitable forstoring electronic instructions), or a machine-readable transmissionmedium such as, but not limited to, any type of electrical, optical,acoustical or other form of propagated signals (e.g., carrier waves,infrared signals, digital signals, etc.).

The algorithms and displays presented herein are not inherently relatedto any particular computer system or other apparatus. Various generalpurpose systems may be used with programs in accordance with theteachings herein, or it may prove convenient to construct morespecialized apparatuses to perform the method operations. The structurefor a variety of these systems appears from the description above. Inaddition, the invention is not described with reference to anyparticular programming language. It will be appreciated that a varietyof programming languages may be used to implement the teachings of theinvention as described herein.

Embodiments of the invention may include various operations as set forthabove or fewer operations or more operations or operations in an orderwhich is different from the order described herein. The operations maybe embodied in machine-executable instructions which cause ageneral-purpose or special-purpose processor to perform certainoperations. Alternatively, these operations may be performed by specifichardware components that contain hardwired logic for performing theoperations, or by any combination of programmed computer components andcustom hardware components.

Throughout the foregoing description, for the purposes of explanation,numerous specific details were set forth in order to provide a thoroughunderstanding of the invention. It will be apparent, however, to oneskilled in the art that the invention may be practiced without some ofthese specific details. Accordingly, the scope and spirit of theinvention should be judged in terms of the claims which follow as wellas the legal equivalents thereof.

1. A method to emulate a system represented by one or more of hardwareportions and software portions, the method comprising: determining,using a processor, whether a subset of the one or more hardware portionsand software portions have been tested; identifying, using a processor,whether the system has performed to a specification based on the testingof the subset of the one or more hardware portions and softwareportions; when the system has not performed to the specification,determining one or more of the hardware and software portions to updatefor retesting.
 2. A method to emulate a system represented by one ormore of hardware portions and software portions, the method comprising:identifying, using a processor, whether the system has performed to aspecification by testing a subset of the one or more hardware portionsand software portions; determining, using a processor, locations in theone or more of hardware portions and software portions associated withthe specification.